1. Field of the Invention
The present invention relates to a semiconductor memory device and a data reading method thereof. Particularly, it relates to a semiconductor memory circuit constituting a logic embedded memory in which a semiconductor memory circuit is embedded on a substrate identical with that for the logic circuit, as well as a data reading method thereof.
2. Description of Related Art
FIG. 10 is an example of a logic embedded memory. A logic circuit 206 and other peripheral circuits (high speed IO circuit 208, AD converter 210, DA converter 212) are disposed on a substrate identical with that for a semiconductor memory device such as DRAM 202 or SRAM 204. For the semiconductor memory circuit in the logic embedded memory described above, high speed operation is required in comparison with existent general-purpose semiconductor memory circuits.
On the other hand, FIG. 11 is a circuit diagram showing an existent semiconductor memory device, for example, in Japanese Laid Open Patent Application No. 2006-278778. In a semiconductor memory device 100, a bit line 104 and a bit line 106 are connected to a sense amplifier 102. A reference cell 110 and a reference cell 120 are connected respectively to the bit line 104 and the bit line 106. The reference cell 110 and the reference cell 120 are connected to a common potential line 108. Writing of the reference potential to the reference cell 110 and the reference cell 120 are conducted through the potential line 108 as to be described later.
The reference cell 110 is constituted with a capacitor 112 and transistors 114, 116. In the same manner, the reference cell 120 is constituted with a capacitor 122 and transistors 124, 126. Word lines 152, 154, 156, and 158 are connected to the gates of the transistors 124, 126, 114, and 116, respectively.
Memory cells 1301 to 130n are connected to the bit line 104. n is an integer of 2 or greater and, for example, 128 or 256. Further, memory cells 1401 to 140n are connected to the bit line 106. Each of the memory cells 1301 to 130n is constituted with the capacitor 132 and the transistor 134. The word lines 1621 to 162n are connected to the gates of the transistors 134 of the memory cells 1301 to 130n respectively. In the same manner, each of the memory cells 1401 to 140n is constituted with the capacitor 142 and the transistor 144. Word lines 1641 to 164n are connected to the gates of the transistors 144 of the memory cells 1401 to 140n, respectively.
The reading operation of the data in the semiconductor memory device 100 is to be described with reference to the timing chart of FIG. 12. In the drawing, the potentials for the word lines 152, 154, 156, 158, 1621, 1641 are represented respectively by lines L152, L154, L156, L158, L1621, and 1641. Reading of data from the memory cell 1301 and the memory cell 1401 continuously is taken as an example in this case.
At first, by activating the word line 152, and thereby turning the transistor 124 on, a reference potential is written to the reference cell 120 through the potential line 108. The reference potential is set, for example, to ½ Vcc (one-half of the power source potential). “Reference potential is written to the reference cell” means to render one end of the capacitor in the reference cell in a state conducted with the potential line by turning, among the transistors constituting the reference cells, the transistor connected to the potential line to on. Then, after turning the transistor 124 to OFF by deactivating the word line 152, the word line 154 and the word line 1621 are activated. Then, the transistor 126 and the transistor 134 are turned on, the potential of the memory cell 1301 and the potential of the reference cell 120 are compared by the sense amplifier 102, by which the data is read from the memory cell 1301.
Successively, by turning the transistor 114 to on by activating the word line 156, the reference potential is written through the potential line 108 to the reference cell 110. Then, after turning the transistor 114 to OFF by deactivating the word line 156, the word line 158 and the word line 1641 are activated. This turns the transistor 116 and the transistor 144 to on and the data is read from the memory cell 1401.
FIG. 13A and the FIG. 13B are graphs showing the change of the potential of the bit line 104, bit line 106, reference cell 120 and memory cell 1301 upon reading the data. FIG. 13A and the FIG. 13B correspond to the cases where the potential read from the memory cell 1301 are high and low, respectively. In the graphs, the ordinate and the abscissa represent the potential V and the time t, respectively. The potentials of the bit line 104, the bit line 106, the reference cell 120, and the memory cell 1301 , are represented by the line L104, the line L106, the line L120 and the line L1301, respectively. Further, the time at which the sense amplifier 102 is activated is represented by an arrow A1, and the time at which equalization of the bit lines 104, 106 is started is represented by an arrow A2.
As shown in FIG. 13A, in a case where the potential read from the memory 130, is high, when the sense amplifier 102 is activated, the potentials of the bit line 104 and the bit line 106 approach high and low, respectively. Correspondingly, the potential of the reference 120 also approaches low. On the other hand, as shown in FIG. 13B, in a case where the potential read from the memory cell 1301 is low, when the sense amplifier 102 is activated, the potentials of the bit line 104 and the bit line 106 approach low and high respectively. Correspondingly, the potential of the reference cell 120 also approaches high.
Such technologies are also shown in Japanese Laid Open Patent Application No. Hei 06(1994)-012860 or Hei 10(1998)-135417.
In the semiconductor memory device 100 as shown in FIG. 11, a plurality (for example, several thousands) of reference cells 110 are connected to a potential line 108. Then, writing of the reference potential to all of the reference cells 110 is conducted simultaneously through the potential line 108. Specifically, in a case where the potential of the reference 110 is low, charges are supplied from the potential line 108 to the reference cell 110. In a case where the potential of the reference cell 110 is high, charges are discharged from the reference cell 110 to the potential line 108.
Accordingly, in a case where the potential of most of the reference cells 110 is low, the potential of the potential line 108 is temporarily put to a state lower than the reference potential Vref as shown by line L108 in FIG. 14A. On the contrary, in a case where the potential of most of the reference cells 110 is high, the potential of the potential line 108 is temporarily put to a state higher than the reference voltage Vref as shown by L108 in FIG. 14B. In FIG. 14A and FIG. 14B, the ordinate and the abscissa represent the potential V and the time t, respectively.
Such a temporarity potential fluctuation of the potential line 108 causes no problem in the low speed operation as in the operation of general-purpose DRAM. In a case where the potential of most of the reference cells 110 is low, the time during which the word line 156 is activated is long as shown in FIG. 11, and the potential of the capacitor 112 (shown by line L112) can therefore be increased to the reference potential Vref. Also in a case where the potential of most of the reference cells 110 is high, the potential of the capacitor 112 can be lowered to the reference potential Vref during activation of the word line 156.
However, during high speed operation as of the semiconductor memory device in the logic embedded memory as an example of which is shown in FIG. 10 the time during which the word line 156 is activated is short as shown in FIG. 14A and FIG. 14B. The word line 156 is therefore deactivated before the potential of the capacitor 112 reaches a predetermined reference potential Vref. Data reading from each of the memory cells 1401 to 140n is thus conducted in a state where the potential of the reference cell 110 is apart from the reference potential Vref. This leads to an error for the data reading.
For example, in a case of reading data from the memory cells 1401 to 140n at the low potential in a state where the potential of the reference cell 110 is lower than the reference potential Vref, the potential difference between both of the cells is decreased. The differential amplification by the sense amplifier 102 may therefore not be conducted exactly. This is identical also in a case of reading the data from the memory cells 1401 to 140n at high potential in a case where the potential of the reference cell 110 is higher than the reference potential Vref.
While the reference cell 110 has been taken as an example in the foregoing descriptions, it will be apparent that the same problem as in the reference cell 110 occurs also for the reference cell 120.